The invention relates to a method for production of a capacitor electrode with an underlying barrier structure in an integrated semiconductor circuit.
The space offered for capacitors in integrated semiconductor circuits, in particular memory circuits, decreases as the integration density increases. In order nevertheless to obtain capacitors having a high capacitance, it has become known to use so-called high-∈ dielectrics as capacitor dielectric. A further objective currently consists in the development of nonvolatile memories (FeRAM) which use ferroelectrics as capacitor material.
These novel capacitor materials generally have to be produced at relatively high process temperatures and using an oxygen-containing process gas. With the use of an oxidizable electrode (for example of polysilicon or tungsten), this would lead to oxidation of the electrode and a resultant decrease in the capacitance of the capacitor. Therefore, it is also necessary to use novel, inert electrode materials, such as e.g. Pt, Ir, Ru.
When such electrode materials are used, there is a problem in that the oxygen diffuses through the chemically stable electrode and a high-resistance blocking oxide layer then builds up at the silicon substrate. In order to prevent this, use is made of a barrier between the electrode and the substrate.
The barrier and also the overlying bottom electrode of the capacitor are usually produced by multiply performing suitable photolithography and etching processes.
A method for production of a thin-film capacitor is described in U.S. Pat. No. 5,366,920. There, the barrier and also the bottom electrode are not produced by a photolithography and etching process, rather an insulation layer is deposited on the substrate, and an opening is introduced into said insulation layer. Afterward, the opening is filled by depositing a barrier layer, an electrode layer, and further layers. In this way, the capacitor is built up layer by layer in the opening of the insulation layer.
U.S. Pat. No. 5,498,561 (European application EP 0 488 283 A2) discloses a memory cell in an integrated circuit. On a substrate, there are arranged a word line and a bit line, and an insulation layer is deposited. A contact-making hole to a drain region of a transistor and a bottom electrode of a capacitor is formed in the insulation layer. A barrier layer is formed above said electrode, said barrier layer being intended to prevent the occurrence of leakage currents which can occur between capacitor electrodes particularly in the case of very thin dielectric layers, particularly in the case of silicon oxide or silicon nitride. In order to form the dielectric layer on the surface of the barrier layer, said surface is etched free beforehand by means of a plasma etching step. A top electrode is formed on the dielectric layer, so that both the barrier layer and the dielectric layer are arranged between the two capacitor electrodes.
A further memory device is disclosed in U.S. Pat. No. 5,959,327, wherein a plurality of transistors are formed on a substrate, an insulation layer being deposited on said transistors. Contact holes to drain regions of the transistors are produced in said insulation layer, which are partly filled with polysilicon and serve as xe2x80x9cplugxe2x80x9d. A thin titanium layer is formed on said polysilicon layer and reacts with the silicon of the polysilicon layer to produce a titanium silicide layer, which serves for lowering the contact resistance between the polysilicon and the titanium nitride layer formed on the titanium silicide layer. The titanium nitride layer serves as silican barrier layer. This prevents diffusion of silicon from the polysilicon layer of the xe2x80x9cplugxe2x80x9d as far as a capacitor formed on the titanium nitride layer and the insulation layer. Before the capacitor is formed, the surface of the titanium nitride layer and of the insulation layer is planarized. The capacitor electrodes are formed horizontally on this planarized surface.
An alternative formation of the capacitor electrodes is described in the U.S. Pat. No. 5,392,189, wherein a further insulation layer is produced on the planarized surface. Holes being etched into the further insulation layer above the silicon barrier layer. The capacitor electrodes with an interposed dielectric layer are formed in a U-shaped manner in the holes.
That configuration of the capacitor electrodes is also disclosed in published international PCT application WO-A 99/27581.
In all of the known devices, the method for production of the capacitor electrodes and the barrier layer is relatively difficult.
It is accordingly an object of the invention to provide a method of producing capacitor electrode with an underlying barrier structure, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which can be carried out simply and with process reliability.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method of producing a capacitor electrode with an underlying barrier structure, the method which comprises:
depositing a barrier layer on a semiconductor substrate;
forming a barrier structure from the barrier layer with a lithographic mask and an etching step;
depositing a barrier incorporation layer covering the barrier structure and surrounding regions;
removing the barrier incorporation layer with chemical mechanical polishing until the barrier structure is uncovered; and
forming the capacitor electrode above the barrier structure.
An important aspect of the invention is that a CMP (chemical mechanical polishing) planarization step is used to produce the barrier structure. CMP is a process step that is simple to perform in semiconductor technology.
In the above-outlined process, the CMP process is used to produce a planarized surface of the barrier incorporation layer and of the barrier structure incorporated therein. The planarized surface is then used as a support for the capacitor electrode that is subsequently to be constructed.
Preferably, in order to form the capacitor electrode, an electrode incorporation layer is deposited above the planarized barrier structure incorporation layer and an electrode patterning hole, which uncovers the barrier structure, is produced in the electrode incorporation layer by means of a lithographic mask and etching step. A layer made of electrode material which fills the electrode patterning hole is then deposited into and surrounding the electrode patterning hole, and, finally, the capacitor electrode is formed from the electrode material layer by CMP.
Accordingly, CMP planarization steps can thus be used both to produce the xe2x80x9cburiedxe2x80x9d barrier structure and to produce the xe2x80x9cbottomxe2x80x9d capacitor electrode. In principle, however, it is also possible for a layer deposition step and a lithographic mask and etching step to be used to form the capacitor electrode in a manner known per se.
With the above and other objects in view there is also provided, in accordance with the invention, a method of producing a capacitor electrode with an underlying barrier structure, the method which comprises:
forming an insulation layer with a contact hole on a semiconductor substrate;
depositing a barrier incorporation layer on the insulation layer and the contact hole;
producing a barrier patterning hole in the barrier incorporation layer with a lithographic mask and an etching step;
depositing a barrier layer into and surrounding the barrier patterning hole;
forming the barrier structure from the barrier layer with a CMP planarization step; and
forming the capacitor electrode.
According to this alternative embodiment, an insulation layer is deposited onto a semiconductor substrate, a contact hole being formed in said insulation layer. A barrier incorporation layer is deposited on said insulation layer and the contact hole. A barrier patterning hole is produced in said barrier incorporation layer, a barrier layer is deposited into and surrounding the barrier patterning hole and a barrier structure is formed from the barrier layer by means of a CMP planarization. Unlike according to the first aspect of the invention, in this process the CMP planarization step is used directly for (lateral) patterning of the barrier layer.
According to a first embodiment variant, the barrier layer can be deposited in such a way that the barrier patterning hole is completely filled. As a result of the subsequent CMP planarization step, the barrier structure incorporation layer with incorporated barrier structure then acquires a planar surface which can serve as a support for the subsequent construction of the capacitor electrode in the manner already described.
In accordance with an added feature of the invention, the method comprises completely filling the barrier patterning hole during the step of depositing the barrier layer.
In accordance with an additional feature of the invention, the capacitor electrode is formed by:
depositing an electrode incorporation layer above the planarized barrier incorporation layer;
producing an electrode patterning hole, uncovering the barrier structure, in the electrode incorporation layer with a lithographic mask and an etching step;
producing a layer of electrode material completely filling the electrode patterning hole in and surrounding the electrode patterning hole; and
forming the capacitor electrode from the electrode material layer by chemical mechanical polishing.
In the alternative, the capacitor electrode is formed by:
depositing a layer of electrode material above the planarized barrier incorporation layer; and
forming the capacitor electrode from the electrode material layer with a lithographic mask and an etching step.
In a second embodiment variant, the barrier layer is deposited in such a way that the bottom and wall of the hole are lined while maintaining a depression. A layer made of electrode material is deposited above the barrier layer. During the subsequent CMP patterning of the barrier layer, the capacitor electrode is simultaneously formed from the overlying electrode material layer. In this embodiment variant, it is advantageous that overall only one photolithography step is sufficient, as a result of which the entire process can be carried out very cost-effectively and in a manner that saves time.
In accordance with another feature of the invention, the upper layer of the contact layer structure is composed of Ir and/or the lower layer of the contact layer structure is composed of Ti.
In accordance with a further feature of the invention, the barrier layer is composed of IrO2.
In accordance with a concomitant feature of the invention, the electrode material layer is composed of Pt.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for production of a capacitor electrode with a barrier structure, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.